FPGA Based Efficient Multiplier for Image Processing Applications Using Recursive Error Free Mitchell Log Multiplier and KOM Architecture

摘要

The Digital Image processing applications like medical imaging, satelliteimaging, Biometric trait images etc., rely on multipliers to improve thequality of image. However, existing multiplication techniques introduce errorsin the output with consumption of more time, hence error free high speedmultipliers has to be designed. In this paper we propose FPGA based RecursiveError Free Mitchell Log Multiplier (REFMLM) for image Filters. The 2x2 errorfree Mitchell log multiplier is designed with zero error by introducing errorcorrection term is used in higher order Karastuba-Ofman Multiplier (KOM)Architectures. The higher order KOM multipliers is decomposed into number oflower order multipliers using radix 2 till basic multiplier block of order 2x2which is designed by error free Mitchell log multiplier. The 8x8 REFMLM istested for Gaussian filter to remove noise in fingerprint image. The Multiplieris synthesized using Spartan 3 FPGA family device XC3S1500-5fg320. It isobserved that the performance parameters such as area utilization, speed, errorand PSNR are better in the case of proposed architecture compared to existingarchitectures